Abordnet

Moore's Law is often misquoted to say that CPU performance doubles every 1.5-2 years.  Let's call that Not-Moore's Law, because it has been close to true for a long while, and a lot of people are relying on it.  It has essentially been provided entirely by process sizes dropping (i.e. the REAL Moore's Law), both by allowing higher clock speeds and by allowing the use of more and fancier logic.  Note that I am talking about the serial performance here. As I understand the problems with power consumption in the 90 nM process, leakage loss has increased from a significant secondary consumer of power to a primary one, and this can only get worse as the process is scaled down to 65 NM.  Now, IBM, AMD, Intel and others have announced forthcoming improvements to alleviate this, but that will only be alleviation.  And, as with all such work, it becomes harder and harder to do as time goes on.  We are already seeing the problem in the apparently relentless increase in power consumption of the highest-performing CPUs. Now, my question is whether we have seen the beginning of the end of Not-Moore's Law? Even if Moore's Law holds, and the process sizes continue to drop, the need to keep the power consumption down will mean that CPUs have to be run slower.  So we could see the doubling time increase from 1.5-2 years to 3-4 years, and perhaps longer.  But will we?  Or are there significant rabbits still hidden in the hat? Regards, Nick Maclaren.

Moore's Law is often misquoted to say that CPU performance doubles every 1.5-2 years.  Let's call that Not-Moore's Law, because it has been close to true for a long while, and a lot of people are relying on it.  It has essentially been provided entirely by process sizes dropping (i.e. the REAL Moore's Law), both by allowing higher clock speeds and by allowing the use of more and fancier logic.  Note that I am talking about the serial performance here. A separate problem, which isn't so very far away, is speed-of-light- in-silicon. Take a McKinley, at just over 400mm^2. So, it's about 20mm from side to side, and that's equivalent to 15GHz in vacuum, or 10GHz at best in silicon. Me, I reckon we're going to see a bifurcation in processor designs. Multiple cores per chip is a current fashion. It started to get established with Power4, and Sun and HP have made announcements. Announcements at IDF included true dual-core Xeons (still with HyperThreading, for 4 virtual processors) and 16 IA-64 cores in Tanglewood. Yes, they'll require gigantic bus bandwidths. Bandwidth can be obtained with money. Latency is harder. Multi-core processors don't have to be tightly-coupled the units on a serial processor do. So they can take advantage of larger dies in bigger processes, and add cores, rather than speed up the clock. There's just more headroom. Serial processors have to be close-coupled (with current ideas) so the speed of light matters, and in a few years, their growth is going to be limited to process improvements, as limited by leakage. So which is going to run faster? Multi-core processors are excellent for the current fashion in application design (web serving). They don't help at all with pure serial software. Many manufacturers are going to be trying hard to convince people that threading is the answer to performance now - which it isn't, at present, but it takes sufficiently long to add that they can hope that threaded software might be available by the time their processors are on sale. Besides, how many marketing people really understand these issues? The salvation for serial processors, oddly enough, might be Microsoft. Since the desktop apps that they do so well aren't nearly as amenable to multi-threading (to speed up their eye candy) as server software is, they're going to keep up the pressure for faster serial processors for a while. They'll have to stop, and start improving efficiency at some point, but that cultural change might be hard to institute. Of course, if someone can invest a way to build a serial processor without being speed-of-light limited, all such predictions are dust. Let's face it, they usually are. But stimulating ideas is worthwhile.

A separate problem, which isn't so very far away, is speed-of-light- in-silicon. Serial processors have to be close-coupled (with current ideas) so the speed of light matters, and in a few years, their growth is going to be limited to process improvements, as limited by leakage. So which is going to run faster? Loosely coupled will always run faster. But there's no reason that processors that execute a single logical thread of execution cannot be loosely coupled. Historical anecdote: Bob Colwell thought that one of the most innovative things about the P6 was that it was a decentralized, decoupled, design, with all of the different pipestages working independently. No central control. So long as branch prediction works and/or you can overlap the time between an incorrect branch misprediction, its detection, and its repar, you can make pipelines longer. Each pipestage communicates locally, to its nearest pipeline neighbours. The problem with designs that are presently on the market is that the individual pipestages are growing big. There are obvious ways to attack that.

But there's no reason that processors that execute a single logical thread of execution cannot be loosely coupled. Historical anecdote: Bob Colwell thought that one of the most innovative things about the P6 was that it was a decentralized, decoupled, design, with all of the different pipestages working independently. No central control. Ah! I didn't know about that detail. OK, so the speed-of-light business is amenable to moderately clever design already. I'll stop worrying about it for a few years.

The salvation for serial processors, oddly enough, might be Microsoft.  Since the desktop apps that they do so well aren't nearly as amenable to multi-threading (to speed up their eye candy) as server software is, they're going to keep up the pressure for faster serial processors for a while. They'll have to stop, and start improving efficiency at some point, but that cultural change might be hard to institute. [...] Could multi-threading in the OS help though? One(!) of the reasons given for BeOS's very good UI response was supposedly the use of threads for just about every aspect of the GUI (combined with the fact that BeBoxes were SMP). Although it may not speed things up on stop-watch tests, the perceived responsiveness could be raised. (Perception of things being in many cases as important as what actually happens.)

Moore's Law is often misquoted to say that CPU performance doubles every 1.5-2 years.  Let's call that Not-Moore's Law, because it has been close to true for a long while, and a lot of people are relying on it.  It has essentially been provided entirely by process sizes dropping (i.e. the REAL Moore's Law), both by allowing higher clock speeds and by allowing the use of more and fancier logic.  Note that I am talking about the serial performance here. As I understand the problems with power consumption in the 90 nM process, leakage loss has increased from a significant secondary consumer of power to a primary one, and this can only get worse as the process is scaled down to 65 NM.  Now, IBM, AMD, Intel and others have announced forthcoming improvements to alleviate this, but that will only be alleviation.  And, as with all such work, it becomes harder and harder to do as time goes on.  We are already seeing the problem in the apparently relentless increase in power consumption of the highest-performing CPUs. Now, my question is whether we have seen the beginning of the end of Not-Moore's Law? Even if Moore's Law holds, and the process sizes continue to drop, the need to keep the power consumption down will mean that CPUs have to be run slower.  So we could see the doubling time increase from 1.5-2 years to 3-4 years, and perhaps longer.  But will we?  Or are there significant rabbits still hidden in the hat? We are definitely seeing the beginning of the end of Not-Moore's law for conventional microprocessor designs.  A clear analysis: http://citeseer.nj.nec.com/agarwal00clock.html The authors basically say that we are beginning to see performance scale sub-linearly with transistor size decreases, whereas it has scaled super-linearly for the entire history of the microprocessor up to this point.  The basic problem is that architects are running out of useful things for all those little transistors to do.  It is clear that highly parallel architectures will be needed in order to take advantage of all the circuit space that will be available 5, 10, 20 years from now.  Exactly how these highly parallel architectures will work is another debate entirely (I have my bets). Cheers, Benjamin






 

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